DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
OpenFive-USB IP Subsystem-USB 3.1 Controller-USB 3.2 Retimer
USB 2.0 Full High Speed Solution | NXP Semiconductors
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
USB2.0 Host Transceiver PHY IP Core
USB 2.0 OTG IP Core | Arasan Chip Systems
HSIC USB 2.0 PHY IP
XPS USB 2.0 Host Controller
USB 2.0 Device Controller for SoC Designs | Cadence IP
USB v2.0 Soft PHY and Device Controller
USB2.0 PHY – Silicon Library Inc.
USB 2.0 Full High Speed Solution | NXP Semiconductors
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Mixed-Signal Verification for USB 2.0 Physical Layer IP
TUSB1210-Q1 data sheet, product information and support | TI.com
USB v2.0 Soft PHY and Device Controller
USB 2.0 Solutions | Arasan Chip Systems
USB2 PHY
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
The USB 2.0 Device IP core | Arasan Chip Systems
USB 2.0 Full High Speed Solution | NXP Semiconductors
